The present invention relates to buffer circuits. More particularly, the present invention relates to buffer circuits that are capable of receiving a reduced voltage input signal and driving an output also with a reduced voltage output signal.
In some circuits or integrated circuits, a buffer circuit may be employed to receive an input signal and sources or sinks enough current to drive an output conductor (e.g., a bus conductor) or the input gate of another circuit responsive to the signal input. A well-known type of buffer circuit is the tri-state buffer circuit. A tri-state buffer circuit has an output terminal that is either tri-state, high, or low. The ability to tri-state buffer circuits is particularly useful when multiple buffer circuits are coupled to the same load since this permits the buffer circuits that are not active in driving the bus to be decoupled therefrom in order to avoid signal contention on the bus.
To facilitate discussion, FIG. 1 illustrates a simplified prior art inverting tri-state buffer circuit 100, including four transistors in series 102, 104, 106, and 108. P-type field-effect transistor (p-FET) 102 is coupled to rail V.sub.DD and conducts only when the Enable signal is high. Note that unless otherwise indicated herein, all transistors are field-effect transistors (FETs). N-type transistor 108 is coupled to ground and also conducts only when the Enable signal is high (i.e., when EnableN signal is low). When the Enable signal is low, both transistors 102 and 108 are off, thereby tri-stating the output.
When the input signal is high and the Enable signal is also high, n-FET 106 and n-FET 108 will conduct to pull the output to ground. Simultaneously, p-FET 104 is off to decouple the output from V.sub.DD. Conversely, when the input signal is low and the Enable signal is high, p-FETs 102 and 104 will conduct to pull the output to V.sub.DD. Simultaneously, n-FET 106 is off to decouple the output from ground. As can be appreciated, the output of inverting tri-state buffer circuit 100 is the inverse of its input value.
Although the buffer circuit of FIG. 1 has been around for a long time, there are disadvantages. For example, since the tri-state buffer circuit 100 inverts its input, a cascading configuration is required to obtain a noninverting tri-state buffer circuit. To cascade, the output of inverting tri-state buffer circuit 100 may be cascaded into the input of another inverting tri-state buffer circuit 100 to obtain a non-inverting tri-state buffer circuit.
Furthermore, the use of four transistors in series in the output stage (e.g., transistors 102, 104, 106, and 108 in series) exacts a heavy penalty in terms of size. This is because each device in the pull up or pull down path must be fairly large in order to permit enough current to traverse the serially-connected devices in these paths. This is because if the devices are small, the amount of current output by the buffer circuit may be too low, which may introduce unacceptable delay when driving the output load to the desired voltage level.
However, the use of large devices increases the capacitive load on the output conductor, which in turn necessitates an even greater amount of power on the part of the driving buffer circuit to drive the output load properly since the driving buffer circuit sees both the capacitance of the output conductor as well as the capacitance of other tri-stated buffer circuits connected to the load.
Another disadvantage of the configuration shown in FIG. 1 relates to the fact that inverting tri-state buffer 100 is generally incapable of functioning as a reduced voltage input/reduced voltage output tri-state buffer circuit. Reduced voltage input refers to input voltages that are lower than the full V.sub.DD supplied to the chip. In some cases, the reduced voltage may be low enough (e.g., 1V) that it approaches the threshold voltage of the transistors (typically at 0.7 V or so). Likewise, reduced voltage output refers to output voltages that are lower than the full V.sub.DD supplied to the chip. Since reduced voltage signals (i.e., signals whose amplitude is within the reduced voltage range) are useful in reducing circuit power consumption, the inability of inverting tri-state buffer 100 to function as a reduced voltage buffer represents a serious shortcoming.
To appreciate the problems encountered in buffering reduced voltage signals, consider the situation wherein the input of inverting tri-state buffer 100 is logically high but is represented by a reduced voltage signal (e.g., around 1 V). In this case, not only does n-FET 106 conduct as expected but p-FET 104 may also be softly on, causing leakage current to traverse p-FET 104 (from V.sub.DD through p-FET 102). The presence of the leakage current degrades the signal on the output of the buffer circuit (and/or greatly increasing power consumption).
FIG. 2 illustrates another prior art tri-state buffer circuit, which is of the noninverting type. However, the non-inverting tri-state buffer circuit 150 is again found to be incapable of functioning as a reduced voltage input/reduced voltage output buffer circuit. To understand the operation of non-inverting tri-state buffer circuit 150 and its shortcoming in this regard, consider the situation when the input signal has a fill voltage range (i.e., from ground to V.sub.DD). When EN signal is low on line 152, p-FET 130 is on to pull node 154 to V.sub.DD and turns off output p-FET 156. Concurrently, node 158 goes high by the operation of inverter 160. The high node 158 turns on n-FET 162 to pull node 164 low, thereby turning off output n-FET 166. Accordingly, output 168 is decoupled from the rest of the buffer circuit when enable signal EN goes low. As can be seen, a low EN signal tri-states buffer circuit 150.
When enable signal EN goes high and input 170 is high (e.g., at V.sub.DD), the high input 170 causes n-FET 172 to conduct. Accordingly, node 164 is pulled to ground, thereby turning off output n-FET 166 and decouples output 168 from ground. At the same time, the high enable signal EN causes n-FET 174 to also conduct. Therefore, node 154 is pulled low. Note that p-FET 176 is off when input 170 is high, which decouples node 154 from V.sub.DD. The low node 154 turns on output p-FET 156 to cause output 168 to be pulled to V.sub.DD. Thus, a high input 170 and high enable signal EN causes output 168 to go high to V.sub.DD.
Conversely, when enable signal EN is high and input 170 is low (e.g., at about ground), the low input 170 causes n-FET 172 to turn off to decouple node 164 from ground. The low input 170 also causes p-FET 176 to turn on. With p-FET 176 turned on, node 154 is pulled high and output p-FET 156 is turned off, thereby decoupling output 168 from V.sub.DD. Since n-FET 174 is already on (due to high enable signal EN), node 164 is pulled high when p-FET 176 conducts, thereby turning on n-FET 166 to pull output 168 to ground. Thus a low input 170 and high enable signal EN causes output 168 to go low.
Non-inverting tri-state buffer circuit 150 is, however, unable to function when it is required to pass a reduced voltage input signal to its output. This deficiency of the prior art buffer circuits arises due, in part, to the fact that the input signal is employed to control one or more transistor gates. When so employed, the reduced voltage range of the input signal causes some p-FETs to be softly on even when the signal is logically high. For example, if the high logic state is represented by a reduced voltage signal (e.g., 1 V versus 2.5 V or higher of the full swing V.sub.DD), the high logic input is represented by having, for example, the reduced voltage of 1V at input 170.
With 1V at input 170, n-FET 172 would be on but p-FET 176 may also be on, albeit a soft on. This is because if V.sub.DD of 2.5 volts is at the source of p-FET 176 and the threshold voltage of p-FET 176 is 0.7V, the presence of 1V at the gate of p-FET 176 will likely cause this transistor to be on softly. In other words, there is leakage current through p-FET 176 when it should be off. When both these transistors conduct, power consumption is unduly increased. With both transistors 172 and 176 on, the voltage at nodes 154 and 164 may be unstable and/or not be sufficiently well defined to turn on p-FET 156 and turn off n-FET 166 to pull output 168 to the desired high logic value.
As can be appreciated from the foregoing, there are desired tri-state buffer circuits, and methods for making same, that can be employed in reduced voltage signaling applications.